A DRAM cell, formed of a transistor and a capacitor, is widely known. It has further become known to use a trench formed in the substrate as the capacitor of the DRAM cell. The advantage of a trench DRAM cell is an increase in area of the plates of the capacitor for a given surface area of the substrate. In constructing an array or subarray of DRAM cells, trench or otherwise, it is common for each of the capacitors in the array or subarray to have a common plate which is in common with the other cells in the array or subarray and have an individual plate which is connected to the transistor of the cell. In a trench DRAM cell, the individual plate can be either inside the trench or outside the trench. If it is outside the trench, there is a difficulty in keeping the individual plates of adjoining cells from diffusing together. If the individual plate is on the inside, there are also problems most of which are common to either approach.
Even with the increased plate area of a trench capacitor, it is still desirable to have more capacitance in the cell capacitor. One way to increase capacitance is to increase the doping level of the area outside the trench. This has the potential disadvantage of adversely affecting the transistors formed in the substrate. The transistors have better performance characteristics if the doping level is lower than that which is optimum for increasing the capacitance of the capacitor. An example in the prior art of addressing this problem is shown in FIG. 1 which shows a portion of a trench cell 10 formed in a substrate 11 which includes an epitaxial layer 12. This approach uses a P channel array formed in an N well 13 with P channel starting material. Epitaxial layer 12 is grown over substrate 11 which began as highly doped P+ silicon. The resulting epitaxial layer 12 of silicon is a lesser doped P silicon which is used for the formation of N channel transistors in the circuits which are peripheral to the array. N well 13 is then formed in a portion of epitaxial layer 12 doped to only N- for improved transistor performance. Well 13 is coupled to a positive voltage, such as 5 volts, which is shown as VDD in FIG. 1. Substrate 11 is coupled to a negative supply terminal such as ground shown in FIG. 1. Well 13 can be pumped to a voltage higher than the positive power supply VDD and, similarly, substrate 11 can be pumped to a more negative voltage as desired for circuit performance. A trench capacitor 14 is formed through N well 13 and epitaxial layer 12 and into substrate 11. Formed in well 13 is a source 16 and a drain 17. Source 16 and drain 17 are the source and drain of the transistor which, along with capacitor 14 form DRAM cell 10. Capacitor 14 is filled with P+ polysilicon 18 which is dielectrically separated from substrate 11, epitaxial layer 12, and well 13 by an oxide layer 19. Alternatively, layer 19 could be an oxide-nitride-oxide sandwich instead of just oxide. In either case, layer 19 forms a dielectric for capacitor 14. One plate of capacitor 14 is polysilicon 18 which is connected to source 16. This connection to source 16 is not shown in FIG. 1 but is generally accomplished with a conductive strap but can also be accomplished by etching down layer 19 prior to filling the trench with polysilicon 18 so that polysilicon 18 is in direct contact with source 16. The other plate is a combination of substrate 11, epitaxial layer 12, and well 13. Most of the contribution to the capacitance of capacitor 14 is from the substrate because it has a much higher doping concentration than epitaxial layer 12. Well 13 will provide very little contribution because it is lightly doped for transistor performance reasons.
Even though well 13 is lightly doped, there is a limit to how lightly it can be doped because of a parasitic MOS transistor formed between epitaxial layer 12 and source 16. Well 13 acts as the channel, polysilicon 18 acts as the gate, and layer 19 acts as the insulator between the gate and channel. Even a leakage current as low as 1 picoamp will remove the charge stored in capacitor 14 before it can be read and refresned. If well 13 is too lightly doped, the threshold voltage of this parasitic transistor is sufficiently low that it will be at least partially conductive and leak at the 1 picoamp rate which ensures loss of data. This lower concentration is desirable because the regular MOS transistors in well have their threshold adjusted by an implant. If the doping level in well 13 is high enough to ensure that the parasitic transistor will not leak off charge from capacitor 14, the threshold adjust implant will not be optimum. The threshold adjust implant is advantageous because, for a given threshold voltage, the body effect is less on a transistor which has had its threshold increased to that give threshold voltage by an implant than on a transistor whose threshold voltage is at the given threshold voltage by virtue of the doping concentration of the well or substrate in which it is formed. The optimum concentration of well 13 is sufficiently low that there would be leakage through the parasitic transistor of sufficient magnitude to destroy cell data, especially when doping variations due to manufacturing variations are taken into account. Process variations during the fabrication of the integrated circuit will result in even lower doping concentrations for some devices. This is handled by raising the target concentration which will thus raise the nominal doping concentration even further beyond the optimum concentration for well 13.